In a wireless communication system, a transmitted signal may travel through multiple propagation paths so that the received signal is a composite of multiple time-shifted versions of the signal. The different time-shifted versions of the transmitted signal, received by the receiver, referred to herein as signal images, suffer from different phase and attenuation effects due to effects of the propagation channel. The multiple time-shifted signal images combine in an unpredictable manner resulting in frequency-dependent fading.
Wireless communication devices for Direct Sequence Code Division Multiple Access (DS-CDMA) systems, such as Wideband CDMA (WCMA)/High Speed Packet Access (HSPA) systems and cdma2000 systems, typically employ an equalizer to combat signal fading due to multi-path propagation. The goal of the equalizer is to detect the individual signal images and combine them coherently to improve the signal quality. A delay processor processes the received signal to identify the multi-path propagation delays corresponding to the individual signal images. Generally, the signal powers of the received signal samples are estimated and a power delay profile (PDP) over a defined search window is generated that describes the signal power as a function of delay. The delays corresponding to the strongest signal images will appear as peaks in the PDP.
To effectively mitigate signal fading, a CDMA receiver needs accurate estimates of the delays associated with the signal images in order to align and coherently combine the signal images. Accurate estimation of the delays starts with accurate power estimates of the received signal samples. The power estimates used for delay estimation may also be used for other purposes, such as Minimum Mean Squared Error (MMSE) channel estimation and demodulation.
Traditional power estimation is performed on a per-delay basis. Channel estimates for a given delay are coherently combined over a range of symbol periods and averaged. The powers of the average channel estimates are then computed, optionally accumulated non-coherently, and averaged to obtain the power estimate. The estimation variance is affected by the number of terms in both averaging steps, while the estimation bias for each delay is primarily determined by the length in time of the temporal accumulation window used for coherent averaging. The estimation bias is due in part to power leakage from strong delays into weak delays, in terms of signal power or magnitude, and in part to other interference leaking into all delays.
When the permissible coherent averaging window is short, e.g. at high vehicular speeds, the resulting estimation bias of the individual power estimates may be large. A large bias in the power estimates makes it difficult to reliably detect the delay structure or the delay spread, which will result in a suboptimal delay configuration of the equalizer and reduced demodulation performance. Using biased average power estimates for MMSE channel estimate scaling may also lead to over-estimating the quality of the initial channel estimates and insufficient suppression of noise.
U.S. published patent application US2005/0152436 (issued as U.S. Pat. No. 7,362,792) discloses one approach to reducing bias in individual power estimates due to power leakage between delays. A noise floor power estimate is computed by looking at the “weak” delays, and that noise floor power estimate is subtracted from the power estimates associated with other delays. The power estimates will thus have a reduced bias for the weaker delays, but the bias for the strong delays may be increased. Furthermore, the noise floor power estimate itself is inherently biased, so heuristic corrective scaling is used to correct for the bias.
Thus, a need remains for a power estimation method that can lower the bias component in the power estimates of the received signal samples for all delays and that does not rely on heuristic correction factors.